МІНІСТЕРСТВО ОСВІТИ І НАУКИ УКРАЇНИ
НАЦІОНАЛЬНИЙ УНІВЕРСИТЕТ “ЛЬВІВСЬКА ПОЛІТЕХНІКА”
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Лабораторна робота №3
з дисципліни "Основи проектування цифрових засобів на ПЛІС"
Тема: РОЗРОБКА КОНВЕЄРНОГО ПРОЦЕСОРА
Мета роботи: розробити конвеєрний процесор.
Функція КОП: 5*a*b + c*d
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Рис. 1. Реалізована схема.
Код конвеєрного процесора
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity gvv_pipeline_mult is
Port ( gvv_clk : in STD_LOGIC;
gvv_reset : in STD_LOGIC;
gvv_a : in STD_LOGIC_VECTOR (7 downto 0);
gvv_b : in STD_LOGIC_VECTOR (7 downto 0);
gvv_d : in STD_LOGIC_VECTOR (7 downto 0);
gvv_y : out STD_LOGIC_VECTOR (15 downto 0));
end gvv_pipeline_mult;
architecture Behavioral of gvv_pipeline_mult is
constant WIDTH: integer:=8;
signal gvv_a1_reg, gvv_a2_reg, gvv_a3_reg, gvv_a4_reg, gvv_a5_reg, gvv_a6_reg : std_logic_vector(WIDTH-1 downto 0);
signal gvv_a0, gvv_a1_next, gvv_a2_next, gvv_a3_next, gvv_a4_next, gvv_a5_next, gvv_a6_next : std_logic_vector(WIDTH-1 downto 0);
signal gvv_b1_reg, gvv_b2_reg, gvv_b3_reg, gvv_b4_reg, gvv_b5_reg, gvv_b6_reg: std_logic_vector(WIDTH-1 downto 0);
signal gvv_b0, gvv_b1_next, gvv_b2_next, gvv_b3_next, gvv_b4_next, gvv_b5_next, gvv_b6_next : std_logic_vector(WIDTH-1 downto 0);
signal gvv_bv0, gvv_bv1, gvv_bv2, gvv_bv3, gvv_bv4, gvv_bv5, gvv_bv6, gvv_bv7 : std_logic_vector(WIDTH-1 downto 0);
signal gvv_bp0, gvv_bp1, gvv_bp2, gvv_bp3, gvv_bp4, gvv_bp5, gvv_bp6, gvv_bp7 : unsigned(2*WIDTH - 1 downto 0);
signal gvv_pp1_reg, gvv_pp2_reg, gvv_pp3_reg, gvv_pp4_reg, gvv_pp5_reg, gvv_pp6_reg, gvv_pp7_reg : unsigned(2*WIDTH - 1 downto 0);
signal gvv_pp0, gvv_pp1_next, gvv_pp2_next, gvv_pp3_next, gvv_pp4_next, gvv_pp5_next, gvv_pp6_next, gvv_pp7_next: unsigned(2*WIDTH - 1 downto 0);
signal gvv_d1_reg, gvv_d2_reg, gvv_d3_reg, gvv_d4_reg, gvv_d5_reg, gvv_d6_reg : std_logic_vector(WIDTH-1 downto 0);
signal gvv_d0, gvv_d1_next, gvv_d2_next, gvv_d3_next, gvv_d4_next, gvv_d5_next, gvv_d6_next : std_logic_vector(WIDTH-1 downto 0);
signal gvv_dpp1_reg, gvv_dpp2_reg, gvv_dpp3_reg, gvv_dpp4_reg, gvv_dpp5_reg, gvv_dpp6_reg, gvv_dpp7_reg : unsigned(2*WIDTH - 1 downto 0);
signal gvv_dpp0, gvv_dpp1_next, gvv_dpp2_next, gvv_dpp3_next, gvv_dpp4_next, gvv_dpp5_next, gvv_dpp6_next, gvv_dpp7_next: unsigned(2*WIDTH - 1 downto 0);
signal gvv_dv0, gvv_dv1, gvv_dv2, gvv_dv3, gvv_dv4, gvv_dv5, gvv_dv6, gvv_dv7 : std_logic_vector(WIDTH-1 downto 0);
signal gvv_dp0, gvv_dp1, gvv_dp2, gvv_dp3, gvv_dp4, gvv_dp5, gvv_dp6, gvv_dp7 : unsigned(2*WIDTH - 1 downto 0);
signal gvv_w : unsigned (15 downto 0);
begin
-- pipeline registers
process(gvv_clk,gvv_reset)
begin
if (gvv_reset = '1') then
gvv_pp1_reg <= (others => '0');
gvv_pp2_reg <= (others => '0');
gvv_pp3_reg <= (others => '0');
gvv_pp4_reg <= (others => '0');
gvv_pp5_reg <= (others => '0');
gvv_pp6_reg <= (others => '0');
gvv_pp7_reg <= (others => '0');
gvv_a1_reg <= (others => '0');
gvv_a2_reg <= (others => '0');
gvv_a3_reg <= (others => '0');
gvv_a4_reg <= (others => '0');
gvv_a5_reg <= (others => '0');
gvv_a6_reg <= (others => '0');
gvv_b1_reg <= (others => '0');
gvv_b2_reg <= (others => '0');
gvv_b3_reg <= (others => '0');
gvv_b4_reg <= (others => '0');
gvv_b5_reg <= (others => '0');
gvv_b6_reg <= (others => '0');
gvv_dpp1_reg <= (others => '0');
gvv_dpp2_reg <= (others => '0');
gvv_dpp3_reg <= (others => '0');
gvv_dpp4_reg <= (others => '0');
gvv_dpp5_reg <= (others => '0');
gvv_dpp6_reg <= (others => '0');
gvv_dpp7_reg <= (others => '0');
gvv_d1_reg <= (others => '0');
gvv_d2_reg <= (others => '0');
gvv_d3_reg <= (others => '0');
gvv_d4_reg <= (others => '0');
gvv_d5_re...
